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Sheet目录3881

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2004 Microchip Technology Inc.

DS30491C-page 171

PIC18F6585/8585/6680/8680

15.3

Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against either the TMR1 register

pair value or the TMR3 register pair value. When a

match occurs, the CCPx pin can have one of the

following actions:

Driven high

Driven low

Toggle output (high-to-low or low-to-high)

Remains unchanged

The action on the pin is based on the value of control

bits, CCPxM3:CCPxM0. At the same time, interrupt

flag bit, CCPxIF, is set.

When configured to drive the CCP pin, the CCP1 pin

cannot be changed; CCP1 module controls the pin.

15.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

By default, the CCP2 pin is multiplexed with RC1.

Alternately, it can also be multiplexed with either RB3

or RE7. This is done by changing the CCP2MX

configuration bit.

15.3.2

TIMER1/TIMER3 MODE SELECTION

The timer used with each CCP module is selected in

the T3CCP2:T3CCP1 bits of the T3CON register.

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

15.3.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCPx

pin is not affected. Only a CCP interrupt is generated (if

enabled).

15.3.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 resets either

the TMR1 or TMR3 register pair. This allows the CCPR1

Additionally, the CCP2 special event trigger will start an

A/D conversion if the A/D module is enabled.

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the data latch.

Note:

The special event trigger from the CCPx

module will not set the Timer1 or Timer3

interrupt flag bits.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Set Flag bit CCP1IF

Match

RC2/CCP1 pin

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion (CCP2 only)

TMR3H

TMR3L

T3CCP2

CCPR2H CCPR2L

Comparator

T3CCP2

T3CCP1

Output

Logic

Special Event Trigger

Set Flag bit CCP2IF

Match

RC1/CCP2 pin

TRISC<1>

CCP2CON<3:0>

Mode Select

Output Enable

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